June
17th,
2014
An opensource domain specific language embedded in OCaml for designing and testing register transfer level hardware designs.
The HardCaml library provides an API roughly consistent with the structural subset of VHDL and Verilog.
/* Verilog counter */
module counter
#(parameter bits = 8)
(
input clock, clear, enable,
output reg [bits-1:0] q
);
always @(posedge clock)
if (clear) q <= 0;
else if (enable) q <= q + 1;
endmodule(* HardCaml counter *)
let q = reg_fb r_sync enable bits (fun d -> d +: 1)OCaml provides the features to make hardware designs generic. Along the lines of parameters and generate statements in VHDL or Verilog but much, much more powerful.
(* a generic binary tree *)
let rec zip op = function
| [] -> []
| [x] -> [x]
| x::y::t -> (op x y) :: zip op t
let rec tree op = function
| [] -> failwith "unexpected"
| [x] -> x
| x -> tree op (zip op x)
(* an adder tree *)
let adder_tree = tree (+:)